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""#$ %$ $ &'( )$*+ + ! ## ,-" #,. ,/"/. 0 /"*11# "/#,#. ##, ." 1#$ ? ? ? ? ? internal memory - character generator rom : 8320 bits - character generator ram : 512 bit - display data ram : 80 8 bits for 80 digits ? ? ? ? ? power supply voltage : 3v/5v 10% ? ? ? ? ? supply voltage for display : 0 ~ -5v (v 5 ) ? ? ? ? ? cmos process ? ? ? ? ? 1/8 duty, 1/11 duty or 1/16 duty : selectable - 1/8 duty : 5 7dots format 1 line - 1/11 duty: 5 10 dots format 1 line - 1/16 duty : 5 7dots format 2 line ? ? ? ? ? 80 qfp or bare chip available ? ? ? ? ? display character pattern : - 5 7dots format : 192 kinds - 5 10 dots format : 32 kinds (the special character pattern can be programmable by character generator ram directly.) ? ? ? ? ? a customer character pattern can be programmable by mask option ? ? ? ? ? automatic power on reset function ? ? ? ? ? it is possible to read both character generator and display data ram from mpu ? ? ? ? ? character type dot matrix lcd driver & con -troller ? ? ? ? ? internal driver :16 common and 40 segment signal output ? ? ? ? ? display character format : 5 7 dots + cursor, 5 10 dots + cursor ? ? ? ? ? easy interface with a 4-bit or 8-bit mpu the apu0066 is a dot matrix lcd driver & controller lsi that is fabricated by low power cmos technology. apu0066 rom code package type handling code rom code 001 : standard 002 : customer package type q : qfp y : chip handling code ty : tray e ? ! ""#$ %$ $ &'( )$*+ + + paralle / serial data conversion circuit cursor blink control circuit character generaotr ram (cg ram) 512 bits character generaotr rom (cg rom) 8320 bits data register (dr) input output buffer busy flag instruction register (ir) instruction decoder (id) address counter (ac) display data ram (dd ram) 80 x 8 bits timing generation circuit 16-bit shift rregister common signal driver 5 4 4 8 8 8 8 7 7 7 8 7 8 7 7 16 16 d common signal (c 1 ~ c 16 ) clk 1 m v dd gnd d b 0 ~ db 3 d b 4 ~ db 7 r / w rs e v 1 v 2 v 3 v 4 v 5 power supply for lcd drive 40-bit shift rregister 40-bit latch circuit segment signal driver segment signal (s 1 ~ s 40 ) 40 40 40 5 clk 2 osc 1 osc 2 ? ! ""#$ %$ $ &'( )$*+ + 2 t a = 25 c ? voltage greater than above may damage to the circuit (v dd v 1 v 2 v 3 v 4 v 5 ) symbol parameter rating unit v dd operating voltage -0.3 ~ +7 v v lcd d river s upply voltage v dd - 13.5 ~ v dd + 0.3 v v in input voltage -0.3 ~ v dd + 0.3 v p d power dissipation 500 mw t opr operating temperature -20 to +75 c t stg storage temperature range -30 to +85 c apu0066 symbol parameter test conditions min. typ. max. unit applicable pin v dd operating voltage ? 2.7 3 3.3 v i dd1 ceramic resonator f osc = 250khz ? 0.3 0.5 i dd2 operating current ( ? 1) resistor oscillation external clock operation f osc = 270khz ? 0.17 0.3 ma v ih1 high 1.9 ? v dd v il1 input voltage 1 ? low -0.3 ? 0.4 e, db 0 - db 7 r/w, rs v ih2 high 0.7v dd ? v dd v il2 input voltage 2 ? low ?? 0.2v dd osc 1 v oh1 i oh = -0.1 ma high 2.0 ?? v lh1 output voltage 1 i ol = 0.1ma low ?? 0.4 db 0 - db 7 v oh2 i o = -40 a high 0.8v dd ?? v lh2 output voltage 2 i o = 40 a low ?? 0.2v dd clk1, clk2. m, d vd com com ?? 1 vd seg voltage drop ( ? 2) i o = 0.05ma seg ?? 1.5 v c 1 ~ c 16 s 1 ~ s 40 i lkg input leakage current v in = 0 or v dd -1 ? 1 e i il input low current v dd = 3v (test pull up r) -10 -50 -120 a rs, r/w, db 0 - db 7 f ec frequency( ? 3) 125 250 350 khz duty duty 45 50 55 % t r rise time ?? 0.2 s t f external clock fall time ?? 0.2 s osc 1 f osc internal clock frequency ( ? 3) rf = 75k ? 2% 190 270 350 khz osc 1 , osc 2 v lcd1 1/5 bias 3 ? 10 v lcd2 lcd driving voltage ( ? 4) v dd ? v 5 1/4 bias 3 ? 10 v v 1 ? v 5 note: ? 1 : the supply current value from v dd when the power condition is as follows v dd = 5v, v ss = 0v, v 5 = -2v (when v dd = 5v) v dd = 3v, v ss = 0v, v 5 = -2v (when v dd = 3v) ? 2 : the voltage drop from lcd bias terminals v dd , v 1 , v 4 and v 5 to each common terminal (c 1 ~ c 16 ). and also the voltage drop from lcd bias terminals v dd , v 2 , v 3 and v 5 to each segment terminal (s 1 ~ s 80 ). ? 3 and ? 4 : refer to oscillator circuit and input the voltage listed in the table below to v 1 ~ v 5 . dc characteristics (v dd = 3v 10%, v ss = 0v, t a = -30 ~ 85 c) ? ! ""#$ %$ $ &'( )$*+ + dc characteristics (v dd = 5v 10%, v ss = 0v, t a = -20 ~ 75 c) apu0066 symbol parameter test conditions min. typ. max. unit applicable pin v dd operating voltage ? 4.5 ? 5.5 v ? i dd1 ceramic resonator f osc = 250khz ? 0.55 0.8 i dd2 operating current ( ? 1) resistor oscillation external clock operation f osc = 270khz ? 0.35 0.6 ma ? v ih1 high 2.2 ? v dd v il1 input voltage 1 ? low -0.3 ? 0.6 e, db 0 - db 7 r/w, rs v ih2 high v dd - 1 ? v dd v il2 input voltage 2 ? low -0.2 ? 1 osc 1 v oh1 i oh = -0.205ma high 2.4 ?? v lh1 output voltage 1 i ol = 1.2ma low ?? 0.4 db 0 - db 7 v oh2 i o = -40 a high 0.9v dd ?? v lh2 output voltage 2 i o = 40 a low ?? 0.1v dd clk1, clk2. m, d vd com com ?? 1 vd seg voltage drop ( ? 2) i o = 0.1ma seg ?? 1 v c 1 ~ c 16 s 1 ~ s 40 i lkg input leakage current v in = 0 or v dd -1 ? 1 e i il input low current v dd = 5v (test pull up r) -50 -125 -250 a rs, r/w, db 0 - db 7 f ec frequency ( ? 3) 125 250 350 khz duty duty 45 50 55 % t r rise time ?? 0.2 s t f external clock fall time ?? 0.2 s osc 1 f osc1 internal clock frequency ( ? 3) rf = 91k ? 2% 190 270 350 khz osc 1 , osc 2 v lcd1 1/5 bias 4.6 ? 10 v lcd2 lcd driving voltage ( ? 4) v dd - v 5 1/4 bias 3 ? 10 v v 1 ? v 5 note : ? 1 : applies to the current value flown in terminal v dd when power is input as follows; v dd = 5v, gnd = 0v, v 1 = 3.4v, v 2 =1.8v, v 3 = 0.2v, v 4 = 1.4v and v 5 = -3v. ? 2 : applied to the voltage drop occurring from terminals v dd , v 1 , v 4 and v 5 to each common terminal (c 1 - c 16 ) when 0.1ma is flown in or out to and from all com and seg terminals, and also to voltage drop occurring from terminals v dd ,v 2 , v 3 and v 5 to each seg terminal (s 1 ~ s 40 ). when the output level is at v dd , v 1 , v 2 level , 0.1ma is flown out, while 0.1ma flow in when the output level is at v 3 , v 4 or v 5 level. this occurs when 5v or -5v is input to v dd , v 1 and v 3 or to v 2 , v 4 , and v 5 respectively. ? 3 : oscillator circuit open frequency input resistor circuit external clock circuit r f : 91k ? 2% osc 1 r f osc 2 osc 1 osc 2 ? ! ""#$ %$ $ &'( )$*+ + 3 ? 4 : input the voltage listed in the table below to v 1 - v 5 ? v lcd is the lcd driving voltage, refer to the initial set of the instruction code. duty 1/8, 1/11 1/16 bias 1/4 1/5 power supply v 1 v dd - v lcd / 4 v dd - v lcd / 5 v 2 v dd - v lcd / 2 v dd - 2v lcd / 5 v 3 v dd - v lcd / 2 v dd - 3v lcd / 5 v 4 v dd - 3v lcd / 4 v dd - 4v lcd / 5 v 5 v dd - v lcd v dd - v lcd ac characteristics (v dd = 5v 10%, v ss = 0v, t a = -20 ~ +75 c) 1. write mode rs r/w e v ih1 v il1 t su1 v il1 v ih1 v il1 t h1 t w v il1 t h1 t f v ih1 v il1 v ih1 v il1 t r t su2 t h2 v il1 v ih1 v il1 t c vaild data v ih1 v il1 db 0 ~ db 7 symbol characteristic min. typ. max. unit test pin t c e cycle time 500 - - ns e t r e rise time - - 25 ns e t f e fall time - - 25 ns e t w e pulse width (high, low) 220 - - ns e t su1 r/w and rs set-up time 40 - - ns r/w, rs t h1 r/w and rs hold time 10 - - ns r/w,rs t su2 data set-up time 60 - - ns db 0 ~ db 7 t h2 data hold time 10 - - ns db 0 ~ db 7 ? ! ""#$ %$ $ &'( )$*+ + 2. read mode symbol characteristic min. typ. max. unit test pin t c e cycle time 500 - -ns e t r e rise time - - 25 ns e t f e fall time - - 25 ns e t w e pulse width (high, low) 220 - - ns e t su r/w and rs set-up time 40 - - ns r/w, rs t h r/w and rs hold time 10 - - ns r/w,rs t d data output delay time - - 120 ns db 0 ~ db 7 t dh data hold time 20 - - ns db 0 ~ db 7 rs e v ih1 v il1 t su v ih1 v il1 t h t w t h1 t f v ih 1 v il1 t r t dh v il1 v ih1 v il1 t c vaild data v ih1 v il1 db 0 ~ db 7 r/w v il1 t d v il1 3. interface mode with apu0065, apu0063 symbol characteristic min. typ. max. unit test pin t wckh clock pulse width high 800 - - ns ckl t wckl clock pulse width low 800 - - ns clk t su data set-up time 300 - - ns d t dh data hold time 300 - - ns d t csu clock set-up time 500 - - ns clk t dm m delay time -1000 - 1000 ns m ? ! ""#$ %$ $ &'( )$*+ + & clk 1 t wckh t csu 0.9 v dd 0.9 v dd 0.9 v dd 0.1 v dd clk 2 t csu 0.1 v dd t wckh 0.1 v dd 0.9 v dd t wckl 0.9 v dd 0.1v dd 0.9 v dd 0.1v dd t su t dh 0.9 v dd t dm m d apu0066 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 41 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 65 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 40 s 38 s 37 s 36 s 35 s 34 s 33 s 32 s 31 s 30 s 29 s 28 s 27 s 26 s 25 s 24 s 23 s 22 s 21 s 20 s 19 s 18 s 15 s 14 s 13 s 12 s 11 s 10 s 9 s 8 s 17 s 18 s 7 s 6 s 5 s 4 s 3 s 2 s 1 gnd osc 1 e r/w rs d m v dd clk 2 clk 1 v 5 v 4 v 3 v 2 v 1 osc 2 db 1 db 0 s 39 s 40 c 15 c 14 c 13 c 12 c 11 c 10 c 9 c 8 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 16 db 7 db 6 db 5 db 4 db 3 db 2 ? ! ""#$ %$ $ &'( )$*+ + 4 1 64 69 70 71 72 73 74 75 76 77 78 79 80 65 66 67 68 ( 0 , 0 ) 55 56 53 54 51 52 49 50 63 61 62 59 60 57 58 48 46 47 s 40 c 1 44 45 43 42 chip size : 2670 2192.9 m pad size : 80 80 m 36 35 34 33 32 31 30 29 28 27 26 25 rs d m v dd clk 2 24 40 39 38 37 db 0 e r/w 41 clk 1 v 5 v 4 v 3 v 2 v 1 osc 2 osc 1 db 1 db 2 10 9 12 11 14 13 16 15 2 4 3 6 5 8 7 17 19 18 21 20 22 23 gnd db 3 db 4 db 5 db 6 db 7 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 c 16 s 39 s 38 s 37 s 36 s 35 s 34 s 33 s 32 s 31 s 30 s 29 s 28 s 27 s 26 s 25 s 24 s 23 s 22 s 21 s 20 s 19 s 18 s 17 s 16 s 15 s 14 s 13 s 12 s 11 s 10 s 8 s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 9 apu0066 ? ! ""#$ %$ $ &'( )$*+ + 5 pin no. pin name x y pin no. pin name x y 1s 22 -1,265.00 -1,025.15 41 db 2 1,265.00 1,022.65 2s 21 -1,140.00 -1,031.45 42 db 3 1,140.00 1,031.45 3s 20 -1,015.00 -1,031.45 43 db 4 1,015.00 1,031.45 4s 19 -890.00 -1,031.45 44 db 5 890.00 1,031.45 5s 18 -770.00 -1,031.45 45 db 6 770.00 1,031.45 6s 17 -650.00 -1,031.45 46 db 7 650.00 1,031.45 7s 16 -550.00 -1,031.45 47 c 1 550.00 1,031.45 8s 15 -450.00 -1,031.45 48 c 2 450.00 1,031.45 9s 14 -350.00 -1,031.45 49 c 3 350.00 1,031.45 10 s 13 -250.00 -1,031.45 50 c 4 250.00 1,031.45 11 s 12 -150.00 -1,031.45 51 c 5 150.00 1,031.45 12 s 11 -50.00 -1,031.45 52 c 6 50.00 1,031.45 13 s 10 50.00 -1,031.45 53 c 7 -50.00 1,031.45 14 s 9 150.00 -1,031.45 54 c 8 -150.00 1,031.45 15 s 8 250.00 -1,031.45 55 c 9 -250.00 1,031.45 16 s 7 350.00 -1,031.45 56 c 10 -350.00 1,031.45 17 s 6 450.00 -1,031.45 57 c 11 -450.00 1,031.45 18 s 5 550.00 -1,031.45 58 c 12 -550.00 1,031.45 19 s 4 650.00 -1,031.45 59 c 13 -650.00 1,031.45 20 s 3 770.00 -1,031.45 60 c 14 -770.00 1,031.45 21 s 2 890.00 -1,031.45 61 c 15 -890.00 1,031.45 22 s 1 1,015.00 -1,031.45 62 c 16 -1,015.00 1,031.45 23 gnd 1,140.00 -1,031.45 63 s 40 -1,140.00 1,031.45 24 osc 1 1,265.00 -1,024.55 64 s 39 -1,265.00 1,021.20 25 osc 2 1,270.00 -811.95 65 s 38 -1,270.00 808.05 26 v 1 1,270.00 -691.95 66 s 37 -1,270.00 688.05 27 v 2 1,270.00 -571.95 67 s 36 -1,270.00 568.05 28 v 3 1,270.00 -451.95 68 s 35 -1,270.00 448.05 29 v 4 1,270.00 -351.95 69 s 34 -1,270.00 348.05 30 v 5 1,270.00 -251.95 70 s 33 -1,270.00 248.05 31 clk 1 1,270.00 -151.95 71 s 32 -1,270.00 148.05 32 clk 2 1,270.00 -51.95 72 s 31 -1,270.00 48.05 33 v dd 1,270.00 48.05 73 s 30 -1,270.00 -51.95 34 m 1,270.00 148.05 74 s 29 -1,270.00 -151.95 35 d 1,270.00 248.05 75 s 28 -1,270.00 -251.95 36 rs 1,270.00 348.05 76 s 27 -1,270.00 -351.95 37 r/w 1,270.00 448.05 77 s 26 -1,270.00 -451.95 38 e 1,270.00 568.05 78 s 25 -1,270.00 -571.95 39 db 0 1,270.00 688.05 79 s 24 -1,270.00 -691.95 40 db 1 1,270.00 808.05 80 s 23 -1,270.00 -811.95 ? ! ""#$ %$ $ &'( )$*+ + pin (no) input / output name description interface v dd (33) for logical circui t (+5v 10% ) v ss (gnd) (23) operating voltage 0v (gnd) v 1 - v 5 (26 - 30) power vegetative supply voltage bias voltage level for lcd driving power supply s 1 - s 40 (22 - 1, 80 - 63) output segment output segment signal output for lcd driving lcd c 1 - c 16 (47 - 62) output common output common signal output for lcd driving lcd osc 1 , osc 2 (24) (25) input (osc 1 ) output (osc 2 ) oscillator both pins connected to rf resistor or ceramic resonator for internal oscillator circuit. in case of external frequency use only, the frequency is input to (osc 1 ) terminal. resistor or ceramic resonator clk 1 (31) data latch clock clock output terminal for the serially transferred data to be latched to the driver. clk 2 (32) data shift clock clock output terminal used when d terminal data output shifts the inside of the driver. m (34) alternated signal for lcd driver output the alternating signal to convert lcd drive waveform to ac character pattern data, which is corresponding, to each common signal, is supplied to driver serially. high selection d (35) output display data interface low non selection e (38) enable start enable signal to read or write the data apu0065 or apu0063 r/w signal input is used to select the read/write mode high read mode r / w (37) read / write low write mode register selection input high data register (for read and write) rs (36) input register select low instruction register (for write), busy flag, address counter (for read) mpu db 0 - db 7 (39 - 46) input / output data interface used for data transfer between the mpu and apu0066. these terminals are for data bus with bi-directional three-state. initial 4 bit (db 0 - db 3 ) are not used during 4 bit operation (db 7 can be used as a busy flag) anpec electronics corp. head office : 5f, no. 2 li-hsin road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 7f, no. 137, lane 235, pac chiao rd., hsin tien city, taipei hsien, taiwan, r. o. c. tel : 886-2-89191368 fax : 886-2-89191369 !"#$%$%&'($ ? ! ""#$ %$ $ &'( )$*+ + ") * input / output logic diagram applicable pin input no pull up rs, r / w with pull up clk 1 , clk 2 , m, d input db 0 ~ db 7 input / output e v do v do v do v do v do v do data v do ? ! ""#$ %$ $ &'( )$*+ + + +,- command rs r / w db7 db6 db5 db4 db3 db2 db1 db0 execution time (fosc=250khz) remark display clear lllllllllh 1.64ms return home llllllllhx 1.64mscursor move to first digit entry mode set lllllllhi / dsh 40 s i / d : set cursor move direction h : increase l : decrease sh : specifies shift of display h : display is shifted l : display is not shifted display on / off llllllhdcb 40 s display h : display on l : display off cursor h : cursor on l : cursor off blinking h : blinking on l : blinking off shift lllllh s / c r / l xx 40 s sc : h : display shift l : cursor move r/l : h : right shift l : left shift set function llllhdlnfxx 40 s dl : h : 8 bits interface l : 4 bits interface n : h : 2 line display l : 1 line display f : h : 5 10 dots l : 5 7 dots set cg ram address lllh cg ram address (corresponds to cursor address) 40 s cg ram data is sent and received after this setting set dd ram address l l h dd ram address 40 s dd ram data is sent and received after this setting write data h l writ data 46 s write data into dd or cg ram read data h h read data 46 s read data from dd or cg ram read busy flag & address lhbf address counter used for both dd & cg ram address 0 s bf : h : busy l : ready ? reads bf indication internal operating is being performed. ? reads address counter contents ? ! ""#$ %$ $ &'( )$*+ + 2 !" 1. lcd panel : 8 character 1 line character format ; 5 7 dots + 1 cursor line (1/4 bias, 1/8 duty) apu0066 s 1 s 40 c 1 c 8 ........... ............................................ 2. lcd panel : 8 character 1 line character format ; 5 10 dots + 1 cursor line (1/4 bias, 1/8 duty) apu0066 s 1 s 40 c 1 c 11 ........................................................ ............... ................ ? ! ""#$ %$ $ &'( )$*+ + 3. lcd panel : 8 character 2 line character format ; 5 7 dots + 1 cursor line (1/5 bias, 1/16 duty) apu0066 s 1 c 1 s 40 ................................ ....... ...... ...................................... c 8 c 9 c 16 4. lcd panel : 16 character 1 line character format ; 5 7 dots + 1 cursor line (1/5 bias, 1/16 duty) apu0066 c 1 ................. ................. ...... ........ ........ c 8 s 1 s 40 c 9 c 16 ? ! ""#$ %$ $ &'( )$*+ + 3 5. lcd panel : 4 character 2 line character format ; 5 7 dots + 1 cursor line (1/4 bias, 1/8 duty) apu0066 s 21 s 1 s 20 c 1 c 8 s 40 ............ ........ ........ ........ ............ apu0066 v 2 v 3 v 1 v dd v 4 v 5 rrrr v dd (+5v) (-5v) or gnd apu0066 v 2 v 3 v 1 v dd v 4 v 5 rrrr v dd (+5v) (-5v) or gnd r ? ! ""#$ %$ $ &'( )$*+ + |
Price & Availability of APU0066-002YE-TY
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